1. Field of the Invention
The present invention relates to an image reading apparatus for optically scanning an original to read image data. More particularly, it relates to an image reading apparatus for used in a digital copying machine or scanner or the like.
2. Description of Related Art
A Conventional image reading apparatus is designed for optoelectrically converting a reflected light on an original into an analog image signal with the use of a linear image sensor such as a CCD. The analog image signal is then converted by an A/D converter into a digital image signal which is subjected to relevant image processing. Such a conventional image reading apparatus is schematically shown in FIG. 16. The image reading apparatus comprises a CCD sensor 101, sample hold circuits 102, amplifier circuits 103, A/D converter circuits 104, a channel mixer circuit 105, a timing signal generator circuit 106, and a phase control circuit 107. While the CCD sensor 101 is of an odd/even (pixel) simultaneously parallel output type, the sample hold circuits 102, the amplifier circuits 103, and the A/D converter circuits 104 are paired for handling odd pixels and even pixels.
The CCD sensor 101 is a solid-state imaging device driven with a combination of transfer clock signal TR, reset pulse signal RS, and shift pulse signal SF. The timing signal generator circuit 106 generates and distributes to each circuit a variety of signals which are different in the pulse width and the phase length, including the transfer clock signal TR, the shift pulse signal SF, the reset pulse signal RS, a sample-hold pulse signal SH, an A/D clock signal AD, and a pixel clock signal PE. The sample-hold circuit 102 is responsive to a signal output duration of the CCD sensor 101 for sampling and holding the analog image signal of a stable period in synchronization with each trailing edge of a sample-hold pulse signal SH. The channel mixer circuit 105 combines the odd and even outputs of the two A/D converter circuits 104 and releases as a image data in synchronization with each leading edge of the pixel clock signal PE. The phase control circuit 107 finely adjusts (in nanoseconds) the phase length of both the reset pulse signal RS and the sample-hold pulse signal SH generated by the timing signal generator circuit 106.
FIG. 17 is a block diagram of the timing signal generator circuit 106. The timing signal generator circuit 106 comprises a main counter circuit 111, a pair of signal generator circuits 112A, another pair of signal generator circuits 112B, and a delay circuit 113. The main counter circuit 111 generates the pixel clock signal PE, a pulse signal PL, two stop signals TST and RST for negating the output of the transfer clock signal TR and the reset pulse signal RS respectively, and a load signal RD which is released whenever the target pixel in the CCD sensor 101 is changed based on an input clock signal EN inputted as the reference clock signal.
The signal generator circuit 112A is responsive to the input clock signal EN and the load signal RD for generating and releasing the signal which has a desired pulse width and a desired phase length. The signal generator circuit 112A comprises, as shown in FIG. 18, a counter circuit 121, a pulse generator circuit 122, a delay circuit 123A, a delay circuit 123B, a delay circuit 123C, an OR gate 124, and a NOT gate 125. When one period is determined for reading CCD pixels, the pulse width and phase length of generated signals may be selected from {fraction (2/8)} to ⅞ the period and from {fraction (0/8)} to ⅞ the period respectively based on ⅛ the period between the leading edge and the trailing edge of a pulse of the input clock signal EN, as shown in FIG. 19. More specifically, the output signal shown in FIG. 19 has a pulse width of ⅜ the period and a phase length of ⅜ the period.
The counter circuit 121 is responsive to the load signal RD from the main counter circuit 111 for outputting a load value of the load signal RD corresponding to the phase setting determined from a table shown in FIG. 20 delaying by one cycle of the input clock signal EN. Otherwise, the counter circuit 121 continues counting up until the load signal is received again.
The pulse generator circuit 122 compares between the output of the counter circuit 121 and its comparative value corresponding to the pulse width setting based on a table shown in FIG. 21. When the output of the counter circuit 121 is smaller than the comparative value, the output signal is released at “H” level. Otherwise, the output signal is released at “L” level. Meanwhile, the output signal is delayed by two cycles of the input clock signal EN.
The delay circuit 123C delays the output of the pulse generator circuit 122 by three cycles of the input clock signal EN so that the pipeline delay number of the signal generator circuit 112A is equal to eight cycles of the input clock signal EN.
The delay circuit 123A is synchronized with the leading edge of the input clock signal EN and when n is an even number at the phase length of n/8 the period, outputs its input signal delaying by two cycles of the input clock signal EN. When n is an odd number at the phase length of n/8 the period and m is an odd number at the pulse width of m/8 the period, the delay circuit 123A outputs its input signal delaying by three cycles of the input clock signal EN. Otherwise, the output signal is released at “L” level.
The delay circuit 123B is synchronized with the trailing edge of the input clock signal EN and when n is an odd number at the phase length of n/8 the period, outputs its input signal delaying by 2.5 cycles of the input clock signal EN. Otherwise, the output signal is released at “L” level.
FIG. 22 is a block diagram of the signal generator circuit 112B. The signal generator circuit 112B comprises a counter circuit 131, a pulse generator circuit 132, a delay circuit 133A, a delay circuit 133B, a delay circuit 133C, an OR gate 124, a NOT gate 125, a delay circuit 133D, and a selector 137. The three delay circuits 133A, 133B, and 133C are identical to the three delay circuits 123A, 123B, and 123C in the signal generator circuit 112A. In other words, the signal generator circuit 112B is equal to the signal generator circuit 112A plus the delay circuit 133D and the selector 137. The signal generator circuit 112B is responsive to the input clock signal EN, the load signal RD, and the stop signal TST or RST for generating and releasing the signal which has a desired pulse width and a desired phase length and has been stopped outputting for a predetermined signal stop period.
The delay circuit 133D outputs the stop signal TST or RST delaying by two cycles of the input clock signal EN so that the pipeline delay number before the signal is negated at the outside should be equal to eight cycles of the input clock signal EN with reference to counts by the main counter for the CCD sensor.
The selector 137 selects and passes a stop-interval signal STT (may be at either “H” or “L” level and in this example, set to “L” level) when the output of the delay circuit 133D is at “H” level. When the output of the delay circuit 133D is at “L” level, the selector 137 selects and passes the output signal of the delay circuit 133C.
The action of the image reading apparatus having the foregoing arrangement will now be explained. The CCD sensor 101 is entirely driven according to the timing chart shown in FIG. 23. More particularly, when the shift pulse signal SF is turned to “H” level, the charge accumulated in photodiodes in the CCD sensor 101 is entirely transferred on a line-by-line basis to two, odd and even, analog shift registers. As timed with the transfer clock signal TR, the charge is parallelly transferred on a pixel-by-pixel basis to corresponding floating capacitors of the output portion. The potential difference between the capacitors is then amplified and released as the output signal from the CCD sensor 101. The potential difference can be initialized when the reset pulse signal RS is turned to “H” level before the succeeding pixel reading. While the shift pulse signal SF is at “H” level, both the transfer clock signal TR and the reset pulse signal RS remain negated for preventing the generation of noise.
The output signal released from the CCD sensor 101 is then sampled and held in the sample-hold circuit 102 at the timing of a sample-hold pulse SH as shown in FIG. 24. The output signal of the sample-hold circuit 102 is then amplified by the amplifier circuit 103 and converted at the timing of an A/D clock signal AD to a digital signal in the A/D converter circuit 104. The two, odd and even, digital signals are combined at the timing of the pixel clock signal PE in the channel mixer circuit 105. A resultant composite signal is then released from the channel mixer circuit 105 as the read image data.
The actions of the main counter circuit 111, the signal generator circuit 112A, and the signal generator circuit 112B for generating the various signals are also explained. It is assumed that the read image data is processed at 40 MHz. The action of the main counter circuit 111 is first explained referring to FIG. 25. The main counter circuit 111 receives the input clock signal EN as a reference clock signal. The input clock signal EN is frequency divided to form the pixel clock signal PE. Also, the pulse signal PL, the transfer clock stop signal TST, and the reset pulse stop signal RST are generated on the pixel-by-pixel basis from the CCD sensor 101. Upon the target pixel in the CCD sensor 101 being changed, the load signal RD is generated. The output signal of the main counter indicates the position of pixels in the image data at the timing of the pixel clock signal PE. The output signal of the main counter for the CCD sensor is equivalent to the output of the main counter from which the least significant bit is omitted.
The pulse signal PL, the transfer clock stop signal TST, and the reset pulse stop signal RST are then delayed by one CCD pixel (four cycles of the input clock signal EN) from the predetermined position (at 2 shown in FIG. 25) on the main counter for the CCD sensor. The pulse signal PL is further delayed by one CCD pixel in the delay circuit 113 and released as the shift pulse signal SF. The delay by one CCD pixel is necessary for synchronization with the other signals at the same pipeline delay number.
The pipeline delay number before the output signal is released out from the main counter circuit 111 is held to two CCD pixels (four cycles of the pixel clock signal=eight cycles of the input clock signal) for each signal by the action of the two signal generator circuits 112A and 112B. This ensures the synchronization between the output signal of the CCD sensor 101 and the read image data.
The actions of the signal generator circuits 112A and 112B are now explained. Assuming that the pulse width is m/8 the period and the phase length is n/8 the period, the action of the signal generator circuit 112A first is classified into four modes depending on the even and odd of m and n. FIGS. 26 to 29 illustrate timing charts of the four modes of the action of the signal generator circuit 112A. FIG. 26 is the timing chart of the signal generator circuit 112A where the pulse width is {fraction (4/8)} the period (m being an even number) and the phase length is zero the period(n being an even number). FIG. 27 is the timing chart of the signal generator circuit 112A where the pulse width is ⅜ the period (m being an odd number) and the phase length is zero the period(n being an even number). FIG. 28 is the timing chart of the signal generator circuit 112A where the pulse width is {fraction (6/8)} the period (m being an even number) and the phase length is ⅜ the period (n being an odd number). FIG. 29 is the timing chart of the signal generator circuit 112A where the pulse width is ⅜ the period (m being an odd number) and the phase length is ⅜ the period (n being an odd number).
As apparent from FIGS. 26 to 29, the signal generator circuit 112A generates the signal which has a desired pulse width and a desired phase length and is delayed by two CCD pixels (eight cycles of the input clock signal). It is now assumed for detailed description of the action of the signal generator circuit 112A that the pulse width is {fraction (4/8)} the period and the phase length is zero the period as shown in FIG. 26.
Based on the table of FIG. 20, as the phase length is zero the period, the load value is “0”. The output signal of the counter circuit 121 is thus equivalent to the count data “0” delayed by one cycle of the input clock signal EN. And, based on the table of FIG. 21, as the pulse width is {fraction (4/8)} the period, the comparative value is “2”. Accordingly, the pulse generator circuit 122 releases the signal which is at “H” level when the output of the counter circuit 121 is smaller (namely 0 or 1) than the comparative value “2” and has been delayed by two cycles of the input clock signal EN.
The output signal of the pulse generator circuit 122 is delayed again by three cycles of the input clock signal EN in the delay circuit 123C. The output signal of the delay circuit 123C is further delayed by two cycles of the input clock signal EN in the delay circuit 123A. Meanwhile, as the phase length is zero the period, the output signal of the delay circuit 123B remains at “L” level. The OR gate 124 finally determines the state of the output signal of the signal generator circuit 112A from the two output signals of the delay circuits 123A and 123B. The output signal of the signal generator circuit 112A has a pulse width of {fraction (4/8)} the period and a phase length of zero the period as having been delayed by two CCD pixels (eight cycles of the input clock signal EN).
The action of the signal generator circuit 112B is now explained. The action of the signal generator circuit 112B like the signal generator circuit 112A is also classified into four modes depending on the even and odd of m and n at the pulse width of m/8 the period and the phase length of n/8 the period. It is hence assumed for detailed description of the action of the signal generator circuit 112B that the pulse width is ⅜ the period (m being an odd number) and the phase length is ⅜ the period (n being an odd number) as shown in FIG. 30.
Based on the table of FIG. 20, as the phase length is ⅜ the period, the load value is “3”. The output signal of the counter circuit 131 is thus equivalent to the count data “3” delayed by one cycle of the input clock signal EN. And, based on the table of FIG. 21, as the pulse width is ⅜ the period, the comparative value is “1”. Accordingly, the pulse generator circuit 132 releases the signal which is at “H” level when the output of the counter circuit 131 is smaller (namely 0) than the comparative value “1” and has been delayed by two cycles of the input clock signal EN.
The output signal of the pulse generator circuit 132 is delayed again by three cycles of the input clock signal EN in the delay circuit 133C. The output signal of the delay circuit 133C is transferred to the selector 137. Meanwhile, the stop signal TST or RST is delayed by two cycles of the input clock signal EN in the delay circuit 133D and then transmitted to the selector 137. The selector 137 selects and passes the stop-interval signal STT (held at “L” level in this example) when the output signal of the delay circuit 133D is at “H” level. When the output signal is “L” level, the selector 137 selects and passes the output signal of the delay circuit 133C.
The output signal of the selector 137 is received by the delay circuit 133A. As both m and n are odd numbers at the pulse width of m/8 and the phase length of n/8, the output signal of the selector 137 is delayed by three cycles of the input clock signal EN in the delay circuit 133A. The output signal of the selector 137 is also received by the delay circuit 133B. As n is an odd number at the phase length of n/8, the output signal of the selector 137 is delayed by 2.5 cycles of the input clock signal EN in the delay circuit 133B. The OR gate 124 finally determines the state of the output signal of the signal generator circuit 112B from the two output signals of the delay circuits 133A and 133B. The output signal of the signal generator circuit 112B has a pulse width of ⅜ the period and a phase length of ⅜ the period as having been delayed by two CCD pixels (eight cycles of the input clock signal EN).
However, the conventional image reading apparatus has a disadvantage that its model suited for a high-speed machine can hardly be applied to a low or middle speed machine. This may be explained by the fact that when the driving frequency is lowered, the pulse width and phase length of the control signals generated by the signal generator circuits 112A and 112B can hardly be maintained in the controllable accuracy.
For example, if the read image data is processed at 40 MHz, the CCD sensor 101 is driven at a rate of 20 MHz per pixel and its period is 50 ns. The smallest controlling step of the timing signal is thus 6.25 ns (equal to 50 ns/8). If the read image data is processed at 26.67 MHz, the CCD sensor 101 is driven at a rate of 13.33 MHz per pixel and its period is then 75 ns. The smallest controlling step of the timing signal is thus 9.38 ns (equal to 75 ns/8). As apparent, when the same model suited for the high-speed (40 MHz) machine is applied to the low or medium speed (26.67 MHz) machine, the smallest controlling step of the timing signals generated in the signal generator circuits 112A and 112B becomes greater, hence declining the accuracy of signal timing.
Also, when the period for reading in the CCD sensor 101 is increased (the frequency is lowered), the frequency of the input clock signal is also lowered, hence varying the pulse width and phase length of the timing signals generated in the signal generator circuits 112A and 112B.